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DAC
2003
ACM
16 years 7 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
WISE
2009
Springer
16 years 3 months ago
Personalizing the Interface in Rich Internet Applications
Recently, existing design methodologies targeting traditional Web applications have been extended for Rich Internet Application modeling support. These extended methodologies curre...
Irene Garrigós, Santiago Meliá, Sven...
GLVLSI
2005
IEEE
122views VLSI» more  GLVLSI 2005»
16 years 11 days ago
Thermal aware cell-based full-chip electromigration reliability analysis
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson
ISSS
2002
IEEE
148views Hardware» more  ISSS 2002»
15 years 11 months ago
A Case Study of Hardware and Software Synthesis in ForSyDe
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...
Ingo Sander, Axel Jantsch, Zhonghai Lu
ICSM
1998
IEEE
15 years 11 months ago
Identification of Data Cohesive Subsystems Using Data Mining Techniques
The activity of reengineering and maintaining large legacy systems involves the use of design recovery es to produce abstractions that facilitate the understanding of the system. ...
Carlos Montes de Oca, Doris L. Carver