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CDC
2010
IEEE
15 years 1 months ago
Trajectory generation using sum-of-norms regularization
Abstract-- Many tracking problems are split into two subproblems, first a smooth reference trajectory is generated that meet the control design objectives, and then a closed loop c...
Henrik Ohlsson, Fredrik Gustafsson, Lennart Ljung,...
ISCA
2012
IEEE
242views Hardware» more  ISCA 2012»
13 years 9 months ago
Side-channel vulnerability factor: A metric for measuring information leakage
There have been many attacks that exploit side-effects of program execution to expose secret information and many proposed countermeasures to protect against these attacks. Howeve...
John Demme, Robert Martin, Adam Waksman, Simha Set...
DAC
2012
ACM
13 years 9 months ago
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
Moongon Jung, David Z. Pan, Sung Kyu Lim
VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
16 years 7 months ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
16 years 23 days ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra