3879 search results - page 303 / 776 » PyPBS design and methodologies |
143
click to vote
EVOW
1999
Springer
15 years 11 months ago
1999
Springer
This paper describes a new approximate approach for checking the correctness of the implementation of a protocol interface, comparing its lowlevel implementation with its high-leve...
174
click to vote
ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
177
click to vote
CODES
2004
IEEE
15 years 10 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
178
click to vote
DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
157
click to vote
DAC
1995
ACM
15 years 10 months ago
1995
ACM
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...