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PPAM
2005
Springer
16 years 10 days ago
Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP
The ARTiS system, a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems is proposed. ARTiS exploits the SMP architecture to guarant...
Éric Piel, Philippe Marquet, Julien Soula, ...
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 11 months ago
Selective, accurate, and timely self-invalidation using last-touch prediction
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
An-Chow Lai, Babak Falsafi
RTSS
1998
IEEE
15 years 11 months ago
Improved Response-Time Analysis Calculations
Schedulability analysis of fixed priority preemptive scheduled systems can be performed by calculating the worst-case response-time of the involved processes. The system is deemed...
Mikael Sjödin, Hans Hansson
TCOM
2010
195views more  TCOM 2010»
15 years 1 months ago
Coherent and Differential Space-Time Shift Keying: A Dispersion Matrix Approach
Abstract--Motivated by the recent concept of Spatial Modulation (SM), we propose a novel Space-Time Shift Keying (STSK) modulation scheme for Multiple-Input Multiple-Output (MIMO) ...
Shinya Sugiura, Sheng Chen, Lajos Hanzo
IESS
2007
Springer
120views Hardware» more  IESS 2007»
16 years 1 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...