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» Proof-Based System Engineering Using a Virtual System Model
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CODES
2008
IEEE
15 years 8 months ago
Slack analysis in the system design loop
We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by su...
Girish Venkataramani, Seth Copen Goldstein
ISPASS
2009
IEEE
16 years 1 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
CGO
2007
IEEE
16 years 26 days ago
Isla Vista Heap Sizing: Using Feedback to Avoid Paging
Managed runtime environments (MREs) employ garbage collection (GC) for automatic memory management. However, GC induces pressure on the virtual memory (VM) manager, since it may t...
Chris Grzegorczyk, Sunil Soman, Chandra Krintz, Ri...
DIGRA
2003
Springer
15 years 11 months ago
Player Character Design Facilitating Emotional Depth in MMORPGs
How can we create computer games facilitating emotional depth in the playing experience? When entering into a persistent virtual game world the player leaves the body behind. It i...
Mirjam Eladhari, Craig A. Lindley
VEE
2012
ACM
222views Virtualization» more  VEE 2012»
14 years 2 months ago
Unpicking the knot: teasing apart VM/application interdependencies
Flexible and efficient runtime design requires an understanding of the dependencies among the components internal to the runtime and those between the application and the runtime...
Yi Lin, Stephen M. Blackburn, Daniel Frampton