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ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
16 years 1 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
ARC
2007
Springer
169views Hardware» more  ARC 2007»
16 years 1 months ago
Designing Heterogeneous FPGAs with Multiple SBs
Abstract. The novel design of high-speed and low-energy FPGA routing architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. For that purpose,...
Kostas Siozios, Stelios Mamagkakis, Dimitrios Soud...
BPM
2007
Springer
148views Business» more  BPM 2007»
16 years 1 months ago
Requirements-Driven Design and Configuration Management of Business Processes
The success of a business process (BP) depends on whether it meets its business goal as well as non-functional requirements associated with it. BP specifications frequently need to...
Alexei Lapouchnian, Yijun Yu, John Mylopoulos
HPCC
2007
Springer
16 years 1 months ago
Towards a Complexity Model for Design and Analysis of PGAS-Based Algorithms
Many new Partitioned Global Address Space (PGAS) programming languages have recently emerged and are becoming ubiquitously available on nearly all modern parallel architectures. PG...
Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazaw...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
16 years 24 days ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore