Formal and dynamic (simulation, emulation, etc.) verification techniques are both needed to deal with the overall challenge of verification. Ideally, the same specification/tes...
We present tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware. We use JHDL to describe the ...
Laurie A. Smith King, Heather Quinn, Miriam Leeser...
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
—The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with othe...
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...