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ICCD
2004
IEEE
115views Hardware» more  ICCD 2004»
16 years 3 months ago
Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs
Formal and dynamic (simulation, emulation, etc.) verification techniques are both needed to deal with the overall challenge of verification. Ideally, the same specification/tes...
Kelvin Ng, Alan J. Hu, Jin Yang
ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
16 years 3 months ago
Run-Time Execution of Reconfigurable Hardware in a Java Environment
We present tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware. We use JHDL to describe the ...
Laurie A. Smith King, Heather Quinn, Miriam Leeser...
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
16 years 3 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
ICCAD
2008
IEEE
109views Hardware» more  ICCAD 2008»
16 years 3 months ago
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus
—The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with othe...
Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang
ICCAD
2002
IEEE
106views Hardware» more  ICCAD 2002»
16 years 3 months ago
Throughput-driven IC communication fabric synthesis
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
Tao Lin, Lawrence T. Pileggi
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