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LICS
1996
IEEE
15 years 10 months ago
Reactive Modules
We present a formal model for concurrent systems. The model represents synchronous and asynchronous components in a uniform framework that supports compositional (assume-guarantee)...
Rajeev Alur, Thomas A. Henzinger
FPGA
1997
ACM
127views FPGA» more  FPGA 1997»
15 years 10 months ago
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
Amit Chowdhary, John P. Hayes
ICPP
1993
IEEE
15 years 10 months ago
Dependence Analysis and Architecture Design for Bit-Level Algorithms
:. In designing application-specific bit-level architectures and in programming existing bit-level processor arrays, it is necessary to expand a word-level algorithm into its bit-...
Weijia Shang, Benjamin W. Wah
APL
1993
ACM
15 years 10 months ago
APROL: a Hybrid Language
This paper describes the design of a hybrid language which combines the features of an array processing language and lisp dialect in a consistent and useful manner. This language,...
Dennis Holmes, John E. Howland
CONCUR
1993
Springer
15 years 10 months ago
Loop Parallelization in the Polytope Model
During the course of the last decade, a mathematical model for the parallelization of FOR-loops has become increasingly popular. In this model, a (perfect) nest of r FOR-loops is r...
Christian Lengauer