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DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 11 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
ISSS
2002
IEEE
124views Hardware» more  ISSS 2002»
15 years 11 months ago
Timing Analysis of Embedded Software for Speculative Processors
Static timing analysis of embedded software is important for systems with hard real-time constraints. To accurately estimate time bounds, it is essential to model the underlying m...
Abhik Roychoudhury, Xianfeng Li, Tulika Mitra
ICS
2001
Tsinghua U.
15 years 11 months ago
Computer aided hand tuning (CAHT): "applying case-based reasoning to performance tuning"
For most parallel and high performance systems, tuning guides provide the users with advices to optimize the execution time of their programs. Execution time may be very sensitive...
Antoine Monsifrot, François Bodin
ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
15 years 11 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
ESEC
1999
Springer
15 years 11 months ago
Comparison Checking: An Approach to Avoid Debugging of Optimized Code
Abstract. We present a novel approach to avoid the debugging of optimized code through comparison checking. In the technique presented, both the unoptimized and optimized versions ...
Clara Jaramillo, Rajiv Gupta, Mary Lou Soffa