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CGO
2005
IEEE
16 years 6 days ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
ICAC
2005
IEEE
16 years 6 days ago
Myrrh: A Transaction-Based Model for Autonomic Recovery
As software comes under increasing scrutiny for its lack of safety and reliability, numerous static and partially dynamic tools (including model checking) have been proposed for v...
Guy Eddon, Steven P. Reiss
RTA
2005
Springer
16 years 2 days ago
Intruder Deduction for AC-Like Equational Theories with Homomorphisms
Cryptographic protocols are small programs which involve a high level of concurrency and which are difficult to analyze by hand. The most successful methods to verify such protocol...
Pascal Lafourcade, Denis Lugiez, Ralf Treinen
AGILEDC
2003
IEEE
15 years 12 months ago
Agile Development in the old economy
As part of the delivery an automated hub for a postal operator, the Solystic company has to build a complex and feature rich Information System that supports a highly automated pr...
Géry Derbier
ISCA
2002
IEEE
103views Hardware» more  ISCA 2002»
15 years 11 months ago
Efficient Dynamic Scheduling Through Tag Elimination
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
Dan Ernst, Todd M. Austin