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204
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ACMMSP
2006
ACM
247views Hardware» more  ACMMSP 2006»
16 years 25 days ago
A flexible data to L2 cache mapping approach for future multicore processors
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
Lei Jin, Hyunjin Lee, Sangyeun Cho
147
Voted
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
16 years 4 days ago
Area Fill Generation With Inherent Data Volume Reduction
Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low...
Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexande...
ISHPC
2003
Springer
16 years 1 days ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
197
Voted
PODS
2000
ACM
137views Database» more  PODS 2000»
15 years 11 months ago
Query Containment for Data Integration Systems
The problem of query containment is fundamental to many aspects of database systems, including query optimization, determining independence of queries from updates, and rewriting ...
Todd D. Millstein, Alon Y. Levy, Marc Friedman
EUROMICRO
1998
IEEE
15 years 11 months ago
Data Speculative Multithreaded Architecture
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
Pedro Marcuello, Antonio González