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VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
16 years 7 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
VLSID
2007
IEEE
126views VLSI» more  VLSID 2007»
16 years 7 months ago
An ECO Technique for Removing Crosstalk Violations in Clock Networks
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama ...
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
16 years 7 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
16 years 7 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
STOC
2004
ACM
122views Algorithms» more  STOC 2004»
16 years 7 months ago
Estimating the weight of metric minimum spanning trees in sublinear-time
In this paper we present a sublinear time (1+ )-approximation randomized algorithm to estimate the weight of the minimum spanning tree of an n-point metric space. The running time...
Artur Czumaj, Christian Sohler
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