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CGO
2008
IEEE
16 years 1 months ago
Prediction and trace compression of data access addresses through nested loop recognition
This paper describes an algorithm that takes a trace (i.e., a sequence of numbers or vectors of numbers) as input, and from that produces a sequence of loop nests that, when run, ...
Alain Ketterlin, Philippe Clauss
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
16 years 1 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
16 years 1 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
ISCA
2007
IEEE
115views Hardware» more  ISCA 2007»
16 years 1 months ago
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
Indirect branches have become increasingly common in modular programs written in modern object-oriented languages and virtualmachine based runtime systems. Unfortunately, the pred...
Hyesoon Kim, José A. Joao, Onur Mutlu, Chan...
KBSE
2007
IEEE
16 years 29 days ago
Tools for model-based security engineering: models vs. code
We present tools to support model-based security engineering on both the model and the code level. In the approach supported by these tools, one firstly specifies the securitycr...
Jan Jürjens, Yijun Yu
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