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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 11 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
IV
1999
IEEE
91views Visualization» more  IV 1999»
15 years 11 months ago
Triangle Mesh Compression for Fast Rendering
Modern GIS(Geographic Information System) application programs and simulation systems have to handle large datasets for rendering. Currently three dimensional rendering hardware a...
Dong-Gyu Park, Yang-Soo Kim, Hwan-Gue Cho
RTSS
1999
IEEE
15 years 11 months ago
Timing Anomalies in Dynamically Scheduled Microprocessors
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
Thomas Lundqvist, Per Stenström
LCPC
1999
Springer
15 years 11 months ago
Compiling for Speculative Architectures
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, targeting the generated code to a speculative para...
Seon Wook Kim, Rudolf Eigenmann
LCN
1998
IEEE
15 years 11 months ago
High Performance Integrated Network Communications Architecture (INCA)
Current communication subsystem mechanisms within workstation and PC class computers are limiting network communications throughput to a small percentage of the present network da...
Klaus Schug, Anura P. Jayasumana, Prasanth Gopalak...
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