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HIPEAC
2011
Springer
14 years 6 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ICPR
2008
IEEE
16 years 7 months ago
Solving quadratically constrained geometrical problems using lagrangian duality
In this paper we consider the problem of solving different pose and registration problems under rotational constraints. Traditionally, methods such as the iterative closest point ...
Carl Olsson, Anders Eriksson
DAC
2005
ACM
16 years 7 months ago
Locality-conscious workload assignment for array-based computations in MPSOC architectures
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over ...
Feihui Li, Mahmut T. Kandemir
ICML
2004
IEEE
16 years 7 months ago
Learning first-order rules from data with multiple parts: applications on mining chemical compound data
Inductive learning of first-order theory based on examples has serious bottleneck in the enormous hypothesis search space needed, making existing learning approaches perform poorl...
Cholwich Nattee, Sukree Sinthupinyo, Masayuki Numa...
SIGSOFT
2008
ACM
16 years 7 months ago
Marple: a demand-driven path-sensitive buffer overflow detector
Despite increasing efforts in detecting and managing software security vulnerabilities, the number of security attacks is still rising every year. As software becomes more complex...
Wei Le, Mary Lou Soffa
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