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ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
14 years 11 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
BMCBI
2011
14 years 11 months ago
Faster Smith-Waterman database searches with inter-sequence SIMD parallelisation
Background: The Smith-Waterman algorithm for local sequence alignment is more sensitive than heuristic methods for database searching, but also more time-consuming. The fastest ap...
Torbjørn Rognes
HIPEAC
2011
Springer
14 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
PPOPP
2012
ACM
14 years 3 months ago
Deterministic parallel random-number generation for dynamic-multithreading platforms
Existing concurrency platforms for dynamic multithreading do not provide repeatable parallel random-number generators. This paper proposes that a mechanism called pedigrees be bui...
Charles E. Leiserson, Tao B. Schardl, Jim Sukha
ICDCS
2012
IEEE
13 years 10 months ago
eTransform: Transforming Enterprise Data Centers by Automated Consolidation
Abstract—Modern day enterprises have a large IT infrastructure comprising thousands of applications running on servers housed in tens of data centers geographically spread out. T...
Rahul Singh, Prashant J. Shenoy, K. K. Ramakrishna...