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DATE
2009
IEEE
149views Hardware» more  DATE 2009»
16 years 1 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
AINA
2008
IEEE
16 years 22 days ago
WS-BPEL Process Compiler for Resource-Constrained Embedded Systems
Process management and workflow systems play an important role in the composition of services in business as well as automation environments. Processes are designed using tools a...
Hendrik Bohn, Andreas Bobek, Frank Golatowski
SEFM
2008
IEEE
16 years 19 days ago
A Fast Algorithm to Compute Heap Memory Bounds of Java Card Applets
We present an approach to find upper bounds of heap space for Java Card applets. Our method first transforms an input bytecode stream into a control flow graph (CFG), and then ...
Tuan-Hung Pham, Anh-Hoang Truong, Ninh-Thuan Truon...
DATE
2007
IEEE
185views Hardware» more  DATE 2007»
16 years 18 days ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha
ICMCS
2007
IEEE
131views Multimedia» more  ICMCS 2007»
16 years 17 days ago
3D Model Retrieval Based on Depth Line Descriptor
In this paper, we propose a novel 2D/3D approach for 3D model matching and retrieving. Each model is represented by a set of depth lines which will be afterward transformed into s...
Mohamed Chaouch, Anne Verroust-Blondet