Sciweavers

6781 search results - page 948 / 1357
» Processors for Mobile Applications
Sort
View
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
16 years 3 days ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
16 years 2 days ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
CGO
2010
IEEE
15 years 12 months ago
Taming hardware event samples for FDO compilation
Feedback-directed optimization (FDO) is effective in improving application runtime performance, but has not been widely adopted due to the tedious dual-compilation model, the difï...
Dehao Chen, Neil Vachharajani, Robert Hundt, Shih-...
ISCA
1999
IEEE
104views Hardware» more  ISCA 1999»
15 years 11 months ago
Is SC + ILP=RC?
Sequential consistency (SC) is the simplest programming interface for shared-memory systems but imposes program order among all memory operations, possibly precluding high perform...
Chris Gniady, Babak Falsafi, T. N. Vijaykumar
ASPLOS
1998
ACM
15 years 11 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...