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ASPLOS
2006
ACM
15 years 10 months ago
Instruction scheduling for a tiled dataflow architecture
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
172
Voted
DSN
2006
IEEE
15 years 10 months ago
Efficient High Hamming Distance CRCs for Embedded Networks
Cyclic redundancy codes (CRCs) are widely used in network transmission and data storage applications because they provide better error detection than lighter weight checksum techn...
Justin Ray, Philip Koopman
206
Voted
ESTIMEDIA
2006
Springer
15 years 10 months ago
Loop Nest Splitting for WCET-Optimization and Predictability Improvement
This paper presents the influence of the loop nest splitting source code optimization on the worst-case execution time (WCET). Loop nest splitting minimizes the number of executed...
Heiko Falk, Martin Schwarzer
162
Voted
HIPC
2000
Springer
15 years 10 months ago
Instruction Level Distributed Processing
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
James E. Smith
ICS
2000
Tsinghua U.
15 years 10 months ago
Hardware-only stream prefetching and dynamic access ordering
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
Chengqiang Zhang, Sally A. McKee