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ASPLOS
2006
ACM
16 years 24 days ago
A performance counter architecture for computing accurate CPI components
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, J...
IPPS
2003
IEEE
16 years 2 days ago
Flexible CoScheduling: Mitigating Load Imbalance and Improving Utilization of Heterogeneous Resources
Fine-grained parallel applications require all their processes to run simultaneously on distinct processors to achieve good efficiency. This is typically accomplished by space sl...
Eitan Frachtenberg, Dror G. Feitelson, Fabrizio Pe...
183
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INFOCOM
2002
IEEE
15 years 11 months ago
Scheduling Processing Resources in Programmable Routers
—To provide flexibility in deploying new protocols and services, general-purpose processing engines are being placed in the datapath of routers. Such network processors are typi...
Prashanth Pappu, Tilman Wolf
CODES
2006
IEEE
15 years 10 months ago
Automatic phase detection for stochastic on-chip traffic generation
During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently don...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
PUC
2010
80views more  PUC 2010»
15 years 5 months ago
Mobile map interactions during a rendezvous: exploring the implications of automation
Abstract Location awareness can help facilitate a rendezvous of two or more persons. To further enhance the rendezvous experience, we conducted two complementary field studies to ...
David Dearman, Kori M. Inkpen, Khai N. Truong