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DAC
1999
ACM
16 years 7 months ago
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, H...
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
16 years 3 months ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-...
SAMOS
2007
Springer
16 years 28 days ago
Evaluating Large System-on-Chip on Multi-FPGA Platform
This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on...
Ari Kulmala, Erno Salminen, Timo D. Hämä...
DDECS
2006
IEEE
108views Hardware» more  DDECS 2006»
16 years 26 days ago
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo ...
APCSAC
2005
IEEE
16 years 13 days ago
Targeted Data Prefetching
Abstract. Given the increasing gap between processors and memory, prefetching data into cache becomes an important strategy for preventing the processor from being starved of data....
Weng-Fai Wong