Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, H...
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on...
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo ...
Abstract. Given the increasing gap between processors and memory, prefetching data into cache becomes an important strategy for preventing the processor from being starved of data....