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SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
16 years 29 days ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
16 years 26 days ago
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
Praveen Raghavan, José L. Ayala, David Atie...
APPT
2007
Springer
16 years 23 days ago
Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors
It is a great challenge to map network processing tasks to processing resources of advanced network processors, which are heterogeneous and multi-threading multiprocessor System-on...
Zhiyong Yu, Zhiyi Yang, Fan Zhang, Zhiwen Yu, Tuan...
IPPS
2006
IEEE
16 years 18 days ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
UIST
2006
ACM
16 years 16 days ago
RecipeSheet: creating, combining and controlling information processors
Many tasks require users to extract information from diverse sources, to edit or process this information locally, and to explore how the end results are affected by changes in th...
Aran Lunzer, Kasper Hornbæk