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ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 10 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
DATE
2010
IEEE
147views Hardware» more  DATE 2010»
15 years 9 months ago
Detecting/preventing information leakage on the memory bus due to malicious hardware
An increasing concern amongst designers and integrators of military and defense-related systems is the underlying security of the individual microprocessor components that make up ...
Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok ...
ASAP
2008
IEEE
120views Hardware» more  ASAP 2008»
15 years 8 months ago
Lightweight DMA management mechanisms for multiprocessors on FPGA
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
ASIACRYPT
2008
Springer
15 years 8 months ago
Twisted Edwards Curves Revisited
This paper introduces fast algorithms for performing group operations on twisted Edwards curves, pushing the recent speed limits of Elliptic Curve Cryptography (ECC) forward in a ...
Hüseyin Hisil, Kenneth Koon-Ho Wong, Gary Car...
ATC
2008
Springer
15 years 8 months ago
Concepts for Autonomous Control Flow Checking for Embedded CPUs
In this paper, we introduce new concepts and methods for checking the correctness of control flow instructions during the execution of programs in embedded CPUs. Detecting and avoi...
Daniel Ziener, Jürgen Teich
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