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CASES
2007
ACM
15 years 10 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
CASES
2007
ACM
15 years 10 months ago
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
DAC
2010
ACM
15 years 10 months ago
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
Lin Huang, Qiang Xu
RTA
2010
Springer
15 years 10 months ago
Certified Subterm Criterion and Certified Usable Rules
Abstract. In this paper we present our formalization of two important termination techniques for term rewrite systems: the subterm criterion and the reduction pair processor in com...
Christian Sternagel, René Thiemann
FPL
2007
Springer
99views Hardware» more  FPL 2007»
15 years 10 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
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