We study the issue of performance prediction on the SGIPower Challenge, a typical SMP. On such a platform, the cost of memory accesses depends on their locality and on contention ...
Nancy M. Amato, Jack Perdue, Mark M. Mathis, Andre...
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
The switch design for interconnection networks plays an important role in the overall performance of multiprocessors and computer networks. It is therefore crucial to study variou...
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...