Sciweavers

6781 search results - page 1089 / 1357
» Processors for Mobile Applications
Sort
View
IPPS
2007
IEEE
16 years 28 days ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
IPPS
2007
IEEE
16 years 28 days ago
Optimizing Inter-Nest Data Locality Using Loop Splitting and Reordering
With the increasing gap between processor speed and memory latency, the performance of data-dominated programs are becoming more reliant on fast data access, which can be improved...
Sofiane Naci
IPPS
2007
IEEE
16 years 28 days ago
A Multi-Level Parallel Implementation of a Program for Finding Frequent Patterns in a Large Sparse Graph
Graphs capture the essential elements of many problems broadly defined as searching or categorizing. With the rapid increase of data volumes from sensors, many application discipl...
Steve Reinhardt, George Karypis
ISCA
2007
IEEE
117views Hardware» more  ISCA 2007»
16 years 28 days ago
ReCycle: : pipeline adaptation to tolerate process variation
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
Abhishek Tiwari, Smruti R. Sarangi, Josep Torrella...
RTAS
2007
IEEE
16 years 27 days ago
Performance Debugging of Real-Time Systems Using Multicriteria Schedulability Analysis
Most of today’s real-time embedded systems consist of a heterogeneous mix of fully-programmable processors, fixed-function components or hardware accelerators, and partially-pr...
Unmesh D. Bordoloi, Samarjit Chakraborty
« Prev « First page 1089 / 1357 Last » Next »