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» Processor Architectures for Ontogenesis
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ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
16 years 10 days ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...
DAC
2006
ACM
16 years 10 days ago
A systematic method for functional unit power estimation in microprocessors
We present a new method for mathematically estimating the active unit power of functional units in modern microprocessors such as the Pentium 4 family. Our method leverages the ph...
Wei Wu, Lingling Jin, Jun Yang 0002, Pu Liu, Sheld...
PPOPP
2006
ACM
16 years 10 days ago
A case study in top-down performance estimation for a large-scale parallel application
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
Ilya Sharapov, Robert Kroeger, Guy Delamarter, Raz...
CODES
2005
IEEE
16 years 1 hour ago
Microcoded coprocessor for embedded secure biometric authentication systems
We design and implement a cryptographic biometric authentication system using a microcoded architecture. The secure properties of the biometric matching process are obtained by me...
Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhe...
WMPI
2004
ACM
15 years 11 months ago
A localizing directory coherence protocol
User-controllable coherence revives the idea of cooperation between software and hardware in an attempt to bridge the gap between efficient small-scale shared memory machines and m...
Collin McCurdy, Charles N. Fischer