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» Processor Architectures for Ontogenesis
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ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
16 years 19 hour ago
Wire-driven microarchitectural design space exploration
— In this paper, we propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. ...
Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram,...
ISCC
2005
IEEE
120views Communications» more  ISCC 2005»
16 years 16 hour ago
Modular Reference Implementation of an IP-DSLAM
We describe a modular reference implementation of an IPbased DSL access multiplexer (DSLAM). We identify deployment trends and primary tasks a future DSLAM has to offer. The imple...
Christian Sauer, Matthias Gries, Sören Sonnta...
SC
2004
ACM
15 years 12 months ago
Unlocking the Performance of the BlueGene/L Supercomputer
The BlueGene/L supercomputer is expected to deliver new levels of application performance by providing a combination of good single-node computational performance and high scalabi...
George Almási, Siddhartha Chatterjee, Alan ...
ICS
2004
Tsinghua U.
15 years 11 months ago
A dynamic application-driven data communication strategy
The use of semi-Lagrangian formulations in numerical weather predication models (NWP) allows for an increase in time step size. Use of this method can increase performance of thes...
Paul van der Mark, Lex Wolters, Gerard Cats
FPL
2003
Springer
81views Hardware» more  FPL 2003»
15 years 11 months ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby