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» Processor Architectures for Ontogenesis
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FPGA
2009
ACM
201views FPGA» more  FPGA 2009»
16 years 1 months ago
A high-performance FPGA architecture for restricted boltzmann machines
Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of...
Daniel L. Ly, Paul Chow
IPPS
2009
IEEE
16 years 1 months ago
Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
ISCA
2008
IEEE
135views Hardware» more  ISCA 2008»
16 years 27 days ago
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introd...
Xiaoyao Liang, Gu-Yeon Wei, David Brooks
MICRO
2008
IEEE
84views Hardware» more  MICRO 2008»
16 years 27 days ago
A performance-correctness explicitly-decoupled architecture
Optimizing the common case has been an adage in decades of processor design practices. However, as the system complexity and optimization techniques’ sophistication have increas...
Alok Garg, Michael C. Huang
PDP
2008
IEEE
16 years 27 days ago
Scheduling of QR Factorization Algorithms on SMP and Multi-Core Architectures
This paper examines the scalable parallel implementation of QR factorization of a general matrix, targeting SMP and multi-core architectures. Two implementations of algorithms-by-...
Gregorio Quintana-Ortí, Enrique S. Quintana...