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» Processor Architectures for Ontogenesis
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ACSAC
2003
IEEE
15 years 11 months ago
MLS-PCA: A High Assurance Security Architecture for Future Avionics
1 DOD Joint Vision 2020 (JV2020) is the integrated multi-service planning document for conduct among coalition forces of future warfare. It requires the confluence of a number of k...
Clark Weissman
IPPS
2000
IEEE
15 years 11 months ago
On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
Alberto Ferreira de Souza, Peter Rounce
VISUALIZATION
1998
IEEE
15 years 10 months ago
Efficient warping for architectural walkthroughs using layered depth images
This paper presents efficient image-based rendering techniques used in the context of an architectural walkthrough system. Portals (doors and windows) are rendered by warping laye...
Voicu Popescu, Anselmo Lastra, Daniel G. Aliaga, M...
CASES
2007
ACM
15 years 10 months ago
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local...
Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo K...
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn