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» Processor Architectures for Ontogenesis
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FPL
2009
Springer
117views Hardware» more  FPL 2009»
15 years 11 months ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
MICRO
1998
IEEE
108views Hardware» more  MICRO 1998»
15 years 10 months ago
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
SBACPAD
2004
IEEE
97views Hardware» more  SBACPAD 2004»
15 years 8 months ago
IATO: A Flexible EPIC Simulation Environment
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
Amaury Darsch, André Seznec
FCCM
2006
IEEE
101views VLSI» more  FCCM 2006»
16 years 17 days ago
A Type Architecture for Hybrid Micro-Parallel Computers
Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequenti...
Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
DAC
2005
ACM
16 years 7 months ago
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology
In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...