2700 search results - page 241 / 540 » Processor Architectures for Ontogenesis |
131
click to vote
DSD
2002
IEEE
15 years 11 months ago
2002
IEEE
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
164
click to vote
DFT
1994
IEEE
15 years 10 months ago
1994
IEEE
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
160
click to vote
CONPAR
1992
15 years 10 months ago
1992
A major feature of Computer Algebra, and more generally of non-numerical computations, is the dynamical and non-predictable behaviour of the executions. We then understand that st...
162
click to vote
ARC
2006
Springer
15 years 10 months ago
2006
Springer
Abstract. We describe a new approach for creating hardware description language (HDL) specifications for custom instructions, to form part of the instruction-set architecture (ISA)...
209
click to vote
ISCAPDCS
2008
15 years 8 months ago
2008
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...