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» Processor Architectures for Ontogenesis
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DAC
1998
ACM
16 years 7 months ago
Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data
Statistical analysis of bug discovery data is used in the software industry to check the quality of the testing process and estimate the reliability of the tested program. In this...
Yossi Malka, Avi Ziv
DAC
2004
ACM
16 years 7 months ago
A general decomposition strategy for verifying register renaming
This paper describes a strategy for verifying data-hazard correctness of out-of-order processors that implement register-renaming. We define a set of predicates to characterize re...
Hazem I. Shehata, Mark Aagaard
DATE
2007
IEEE
93views Hardware» more  DATE 2007»
16 years 27 days ago
Testing in the year 2020
Testing today of a several hundred million transistor System-on-Chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What will test technology be...
Rajesh Galivanche, Rohit Kapur, Antonio Rubio
ISCAS
2007
IEEE
76views Hardware» more  ISCAS 2007»
16 years 25 days ago
In Vitro Epileptic Seizure Prediction Microsystem
— The architecture and VLSI implementation of an epileptic seizure prediction microsystem are presented. The microsystem comprises a neural recording interface and a seizure pred...
J. N. Y. Aziz, Rafal Karakiewicz, Roman Genov, A. ...
FPL
2007
Springer
105views Hardware» more  FPL 2007»
16 years 21 days ago
An Execution Model for Hardware/Software Compilation and its System-Level Realization
We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then ...
Holger Lange, Andreas Koch