2700 search results - page 237 / 540 » Processor Architectures for Ontogenesis |
217
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ISCAPDCS
2004
15 years 8 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
154
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural speci...
155
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
172
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GECCO
2007
Springer
16 years 21 days ago
2007
Springer
In recent years the computing power of graphics cards has increased significantly. Indeed, the growth in the computing power of these graphics cards is now several orders of magn...
180
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CODES
2006
IEEE
16 years 18 days ago
2006
IEEE
Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequ...