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» Processor Architectures for Ontogenesis
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TCAD
2002
158views more  TCAD 2002»
15 years 6 months ago
Static power modeling of 32-bit microprocessors
The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...
Carlo Brandolese, Fabio Salice, William Fornaciari...
CORR
2010
Springer
66views Education» more  CORR 2010»
15 years 5 months ago
Three-Level Parallel J-Jacobi Algorithms for Hermitian Matrices
The paper describes several efficient parallel implementations of the one-sided hyperbolic Jacobi-type algorithm for computing eigenvalues and eigenvectors of Hermitian matrices. ...
Sanja Singer, Sasa Singer, Vedran Novakovic, Davor...
IAJIT
2010
140views more  IAJIT 2010»
15 years 5 months ago
HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...
Anis Boudabous, Ahmed Ben Atitallah, Lazhar Khriji...
FPL
2010
Springer
146views Hardware» more  FPL 2010»
15 years 4 months ago
Software Managed Distributed Memories in MPPAs
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
Robin Panda, Jimmy Xu, Scott Hauck
EGH
2009
Springer
15 years 4 months ago
Fast minimum spanning tree for large graphs on the GPU
Graphics Processor Units are used for many general purpose processing due to high compute power available on them. Regular, data-parallel algorithms map well to the SIMD architect...
Vibhav Vineet, Pawan Harish, Suryakant Patidar, P....