Sciweavers

2700 search results - page 228 / 540
» Processor Architectures for Ontogenesis
Sort
View
IPPS
1998
IEEE
15 years 10 months ago
Scheduling with Communication Delays and Data Routing in Message Passing Architectures
This work deals with the scheduling problem of a directed acyclic graph with interprocessor communication delays. The objective is to minimize the makespan, taking into account the...
Aziz Moukrim, Alain Quilliot
HPDC
2008
IEEE
16 years 1 months ago
Harmony: an execution model and runtime for heterogeneous many core systems
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
Gregory F. Diamos, Sudhakar Yalamanchili
ISPASS
2005
IEEE
16 years 4 days ago
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications
SIMD extensions are the most common technique used in current processors for multimedia computing. In order to obtain more performance for emerging applications SIMD extensions ne...
Friman Sánchez, Mauricio Alvarez, Esther Sa...
DAC
2005
ACM
15 years 8 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
EMSOFT
2005
Springer
16 years 3 days ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir