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» Processor Architectures for Ontogenesis
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DAC
2009
ACM
15 years 7 months ago
Way Stealing: cache-assisted automatic instruction set extensions
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
16 years 3 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
DDECS
2006
IEEE
95views Hardware» more  DDECS 2006»
16 years 19 days ago
Parallel Memory Architecture for Arbitrary Stride Accesses
—Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is d...
Eero Aho, Jarno Vanne, Timo D. Hämäl&aum...
ISLPED
2006
ACM
140views Hardware» more  ISLPED 2006»
16 years 16 days ago
L-CBF: a low-power, fast counting bloom filter architecture
—An increasing number of architectural techniques rely on hardware counting bloom filters (CBFs) to improve upon the enegy, delay and complexity of various processor structures. ...
Elham Safi, Andreas Moshovos, Andreas G. Veneris
HPCC
2005
Springer
16 years 3 days ago
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
Francisco J. Villa, Manuel E. Acacio, José ...