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» Processor Architectures for Ontogenesis
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HPCA
2008
IEEE
16 years 1 months ago
Prediction of CPU idle-busy activity pattern
Real-world workloads rarely saturate multi-core processor. CPU C-states can be used to reduce power consumption during processor idle time. The key unsolved problem is: when and h...
Qian Diao, Justin J. Song
EUC
2005
Springer
16 years 2 days ago
On Tools for Modeling High-Performance Embedded Systems
Abstract. Most of the new embedded systems require high performance processors at low power. To cater to these needs, most semiconductor companies are designing multi-core processo...
Anilkumar Nambiar, Vipin Chaudhary
ASPLOS
1992
ACM
15 years 10 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
CONCURRENCY
1998
181views more  CONCURRENCY 1998»
15 years 6 months ago
Communication Performance of Java-Based Parallel Virtual Machines
Message passing libraries such as Parallel Virtual Machine PVM and Message Passing Interface MPI provide a common Application Programming Interface API to implement parallel...
Narendar Yalamanchilli, William W. Cohen
DAC
2010
ACM
15 years 5 months ago
An error tolerance scheme for 3D CMOS imagers
A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and an image signal process...
Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, ...