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» Processor Architectures for Ontogenesis
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WOTUG
2007
15 years 7 months ago
C++CSP2: A Many-to-Many Threading Model for Multicore Architectures
Abstract. The advent of mass-market multicore processors provides exciting new opportunities for parallelism on the desktop. The original C++CSP – a library providing concurrency...
Neil Brown
DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 10 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
ERSA
2006
105views Hardware» more  ERSA 2006»
15 years 8 months ago
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
SAMOS
2004
Springer
15 years 12 months ago
Synchronous Transfer Architecture (STA)
This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and ...
Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil...
IFIP
1993
Springer
15 years 10 months ago
Self-Timed Architecture of a Reduced Instruction Set Computer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
Ilana David, Ran Ginosar, Michael Yoeli