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» Processor Architectures for Ontogenesis
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ACSC
2005
IEEE
16 years 5 days ago
A High Performance Kernel-Less Operating System Architecture
Operating Systems provide services that are accessed by processes via mechanisms that involve a ring transition to transfer control to the kernel where the required function is pe...
Amit Vasudevan, Ramesh Yerraballi, Ashish Chawla
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
16 years 3 days ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
SAMOS
2005
Springer
16 years 13 hour ago
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chi...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...
WMPI
2004
ACM
15 years 12 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
ISCA
2003
IEEE
144views Hardware» more  ISCA 2003»
15 years 11 months ago
Half-Price Architecture
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
Ilhyun Kim, Mikko H. Lipasti