2700 search results - page 195 / 540 » Processor Architectures for Ontogenesis |
149
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IPPS
1994
IEEE
15 years 10 months ago
1994
IEEE
Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi...
168
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DSN
2004
IEEE
15 years 10 months ago
2004
IEEE
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
201
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ISCAPDCS
2003
15 years 8 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
167
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JSA
2007
2007
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
15 years 6 months ago
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Ch...
295
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ASPLOS
2009
ACM
16 years 7 months ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...