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» Processor Architectures for Ontogenesis
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ISSS
2002
IEEE
136views Hardware» more  ISSS 2002»
15 years 11 months ago
Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors
This paper presents a new technique for global energy optimization through coordinated functional partitioning and speed selection for embedded processors interconnected by a high...
Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
15 years 10 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
DDECS
2006
IEEE
140views Hardware» more  DDECS 2006»
15 years 10 months ago
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
Zbysek Gajda
EUC
2006
Springer
15 years 10 months ago
Co-optimization of Performance and Power in a Superscalar Processor Design
Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. Th...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
15 years 8 months ago
An integrated performance and power model for superscalar processor designs
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei