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VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
16 years 6 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
HPCA
2004
IEEE
16 years 6 months ago
Understanding Scheduling Replay Schemes
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
Ilhyun Kim, Mikko H. Lipasti
POPL
2005
ACM
16 years 6 months ago
Formal prototyping in early stages of protocol design
Network protocol design is usually an informal process where debugging is based on successive iterations of a prototype implementation. The feedback provided by a prototype can be...
Alwyn Goodloe, Carl A. Gunter, Mark-Oliver Stehr
SIGMOD
2004
ACM
92views Database» more  SIGMOD 2004»
16 years 6 months ago
The Price of Validity in Dynamic Networks
Massive-scale self-administered networks like Peer-to-Peer and Sensor Networks have data distributed across thousands of participant hosts. These networks are highly dynamic with ...
Mayank Bawa, Aristides Gionis, Hector Garcia-Molin...
PODS
2004
ACM
147views Database» more  PODS 2004»
16 years 6 months ago
Flexible Time Management in Data Stream Systems
Continuous queries in a Data Stream Management System (DSMS) rely on time as a basis for windows on streams and for defining a consistent semantics for multiple streams and updata...
Utkarsh Srivastava, Jennifer Widom