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TACAS
2001
Springer
125views Algorithms» more  TACAS 2001»
15 years 11 months ago
Coverage Metrics for Temporal Logic Model Checking
In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complet...
Hana Chockler, Orna Kupferman, Moshe Y. Vardi
HPCA
2000
IEEE
15 years 11 months ago
Coherence Communication Prediction in Shared-Memory Multiprocessors
Abstract—Sharing patterns in shared-memory multiprocessors are the key to performance: uniprocessor latencytolerating techniques such as out-of-order execution and non-blocking c...
Stefanos Kaxiras, Cliff Young
ICCAD
2000
IEEE
99views Hardware» more  ICCAD 2000»
15 years 11 months ago
On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools
The incremental, “construct by correction” design methodology has become widespread in constraint-dominated DSM design. We study the problem of ECO for physical design domains...
Andrew B. Kahng, Stefanus Mantik
CBMS
1998
IEEE
15 years 11 months ago
Lexicon Assistance Reduces Manual Verification of OCR Output
An OCR system chosen for its high recognition rate and low percent of false positives also assigns low confidence values to many characters that are actually correct. Human operat...
Susan E. Hauser, A. C. Browne, George R. Thoma, Al...
VTS
1997
IEEE
86views Hardware» more  VTS 1997»
15 years 11 months ago
Incremental logic rectification
We address the problem of rectifying an incorrect combinational circuit against a given specification. Based on the symbolic BDD techniques, we consider the rectification process,...
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng