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IEEEPACT
2009
IEEE
16 years 1 months ago
DDCache: Decoupled and Delegable Cache Data and Metadata
Abstract—In order to harness the full compute power of manycore processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this p...
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Hua...
SPIRE
2009
Springer
16 years 1 months ago
A Two-Level Structure for Compressing Aligned Bitexts
A bitext, or bilingual parallel corpus, consists of two texts, each one in a different language, that are mutual translations. Bitexts are very useful in linguistic engineering bec...
Joaquín Adiego, Nieves R. Brisaboa, Miguel ...
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
15 years 11 months ago
A general state graph transformation framework for asynchronous synthesis
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekberg...
ICDE
2007
IEEE
143views Database» more  ICDE 2007»
16 years 8 months ago
Hiding in the Crowd: Privacy Preservation on Evolving Streams through Correlation Tracking
We address the problem of preserving privacy in streams, which has received surprisingly limited attention. For static data, a well-studied and widely used approach is based on ra...
Feifei Li, Jimeng Sun, Spiros Papadimitriou, Georg...
DATE
2009
IEEE
140views Hardware» more  DATE 2009»
16 years 1 months ago
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
With the relentless scaling of semiconductor technology, the lifetime reliability of embedded multiprocessor platforms has become one of the major concerns for the industry. If th...
Lin Huang, Feng Yuan, Qiang Xu