2544 search results - page 224 / 509 » Process pipeline scheduling |
177
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ICASSP
2008
IEEE
16 years 1 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
197
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RTAS
2006
IEEE
16 years 18 days ago
2006
IEEE
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
218
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RTSS
2005
IEEE
16 years 5 days ago
2005
IEEE
Abstract— Dynamic voltage scaling (DVS) is a promising technique for battery-powered systems to conserve energy consumption. Most existing DVS algorithms assume information about...
179
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NCA
2003
IEEE
15 years 12 months ago
2003
IEEE
This paper addresses the problem of how to service web requests quickly in order to minimize the client response time. Some of the recent work uses the idea of the Shortest Remain...
178
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ICRA
2000
IEEE
15 years 11 months ago
2000
IEEE
Manufacturing enterprise automation was focused on factory level where scheduling is a key issue in the past. As more and more companies are relying on their business parmers or s...