Sciweavers

6819 search results - page 986 / 1364
» Process Reuse Architecture
Sort
View
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
15 years 12 months ago
Parallel subdivision surface rendering and animation on the Cell BE processor
—Subdivision Surfaces provide a compact way to describe a smooth surface using a mesh model. They are widely used in 3D animation and nearly all modern modeling programs support ...
R. Grottesi, S. Morigi, Martino Ruggiero, Luca Ben...
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
15 years 12 months ago
An analytical method for evaluating Network-on-Chip performance
Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and becom...
Sahar Foroutan, Yvain Thonnart, Richard Hersemeule...
DEXAW
2002
IEEE
167views Database» more  DEXAW 2002»
15 years 11 months ago
Integrating Heterogeneous Data Sources with XML and XQuery
XML has emerged as the leading language for representing and exchanging data not only on the Web, but also in general in the enterprise. XQuery is emerging as the standard query l...
Georges Gardarin, Antoine Mensch, Tuyet-Tram Dang-...
DSD
2002
IEEE
146views Hardware» more  DSD 2002»
15 years 11 months ago
Configurable Memory Organisation for Communication Applications
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done ...
Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivain...
180
Voted
ISSS
2002
IEEE
136views Hardware» more  ISSS 2002»
15 years 11 months ago
Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors
This paper presents a new technique for global energy optimization through coordinated functional partitioning and speed selection for embedded processors interconnected by a high...
Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu