Sciweavers

6819 search results - page 950 / 1364
» Process Reuse Architecture
Sort
View
DAC
2007
ACM
16 years 7 months ago
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift
Statistical behavior of device leakage and threshold voltage shows a strong width dependency under microscopic random dopant fluctuation. Leakage estimation using the conventional...
Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
DAC
1998
ACM
16 years 7 months ago
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?
Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test ci...
Alexander Grießing, Paolo Ienne
DAC
2001
ACM
16 years 7 months ago
Automated Pipeline Design
The interlock and forwarding logic is considered the tricky part of a fully-featured pipelined microprocessor and especially debugging these parts delays the hardware design proce...
Daniel Kroening, Wolfgang J. Paul
DAC
2001
ACM
16 years 7 months ago
Re-Configurable Computing in Wireless
Wireless communications requires a new approach to implement the algorithms for new standards. The computational demands of these standards are outstripping the ability of traditi...
Bill Salefski, Levent Caglar
DAC
2002
ACM
16 years 7 months ago
A general probabilistic framework for worst case timing analysis
CT The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a...
Michael Orshansky, Kurt Keutzer