6819 search results - page 929 / 1364 » Process Reuse Architecture |
179
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ISCA
1994
IEEE
15 years 11 months ago
1994
IEEE
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
204
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ISCAS
1994
IEEE
15 years 11 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
274
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DAC
1994
ACM
15 years 11 months ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
145
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DAC
1994
ACM
15 years 11 months ago
1994
ACM
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
234
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ICPIA
1992
15 years 11 months ago
1992
Abstract. Octrees o er a powerful means for representing and manipulating 3-D objects. This paper presents an implementation of octree manipulations using a new approach on a share...