6819 search results - page 344 / 1364 » Process Reuse Architecture |
162
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ISCAS
2003
IEEE
16 years 1 days ago
2003
IEEE
A motion adaptive de-interlacing algorithm and its hardware architecture are presented in this paper. It consists the directional interpolation - ELA with median processing, and 4...
202
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EUROMICRO
1999
IEEE
15 years 11 months ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
185
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VLDB
2000
ACM
15 years 10 months ago
2000
ACM
In this paper, we describe a novel Web query processing approach with learning capabilities. Under this approach, user queries are in the form of keywords and search engines are e...
196
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ICASSP
2010
IEEE
15 years 7 months ago
2010
IEEE
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient managem...
204
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BIS
2010
15 years 4 months ago
2010
Inter-organizational B2B systems are most likely tending to change their business requirements over time - e.g. establishing new partnerships or change existing ones. The problem i...